An accelerator can be impressive on a specification sheet and still be difficult to manufacture as a profitable system. Compute dies, memory, interconnects, assembly, testing and cooling have to work together. An improvement in one part does not automatically increase shipments of the finished product.
The useful unit of analysis is therefore the qualified package, not the isolated transistor. This report separates what packaging technologies do from the economic questions their manufacturers and customers still need to answer. Its thesis is an analytical one: the most valuable supplier is often the supplier that improves reliable system output, rather than the supplier advertising the most ambitious component specification.
Architecture
01 / Integration changes the unit of competition
A faster component matters only when the system can feed, connect and cool it.
TSMC describes CoWoS as a family of advanced 2.5D packaging technologies for integrating logic and memory. Its separate SoIC offering addresses three-dimensional silicon stacking. These are related tools for system integration, rather than interchangeable names for a single manufacturing step. Their existence matters because performance increasingly depends on connections between components as well as computation within them.12
An engineering team can partition a design across several dies, reuse some functions and place memory close to compute. But a package also becomes a physical agreement among electrical, mechanical and thermal constraints. The practical question is whether that agreement remains robust through production, installation and ordinary operating stress.
Our interpretation is that a chiplet strategy shifts part of the competitive contest into integration. A smaller die may be easier to manufacture, yet a system containing several dies creates more interfaces to characterize. Comparing only the cost of the individual dies misses the cost of bringing the assembled product through its final acceptance tests.
| Layer | What it contributes | What must be demonstrated |
|---|---|---|
| Compute die | Useful arithmetic and control | Performance under a representative workload |
| Memory and interconnect | Data delivery between components | Bandwidth, latency and signal integrity |
| Package and assembly | Physical integration | Repeatable yield and reliability |
| System qualification | A deployable product | Thermal behavior and final test coverage |
Manufacturing
02 / Yield compounds across the assembly
A simple model reveals why a late failure can be expensive.
Imagine a package assembled from four pretested dies. For an intentionally simplified calculation, suppose each die has a 98% probability of remaining acceptable through integration and the assembly process succeeds 95% of the time. If those events were independent, the combined probability would be 0.98⁴ × 0.95, or about 87.6%. Raising each die probability to 99% increases the result to about 91.3%.
These figures are invented assumptions, not estimates of CoWoS, SoIC or any commercial product. Real flows can include screening, rework, redundancy and correlated failures. The model is useful because it exposes a question that a headline wafer-start figure cannot answer: how much of the input becomes acceptable output?
If 1,000 identical assemblies enter the simplified flow, the two assumptions imply roughly 876 versus 913 acceptable packages. The difference is about 37 units before any change to the nominal arithmetic performance of the design. Whether that improvement justifies a higher component or testing cost depends on the value of the finished package and the expense of failed assemblies.
Small yield changes can alter finished output
View chart data · acceptable packages / 1,000 starts
| Label | Value |
|---|---|
| 98% per die | 876.2 |
Interoperability
03 / An interface standard is a starting point
Common connections reduce one kind of friction without eliminating qualification.
The UCIe Consortium defines a package-level die-to-die interconnect covering physical interfaces, protocols, a software model and compliance testing. Its published specification descriptions include reliability, manageability and test-related capabilities. That is a concrete effort to make components easier to combine across an ecosystem.3
A standard can make the boundary between two dies more predictable. It cannot, on its own, establish that every possible combination meets a particular product's power envelope, temperature limits or service-life requirements. Our due-diligence distinction is between interface compatibility and qualified product compatibility. The first is necessary for many designs; the second is what the customer ultimately buys.
For an investor or procurement team, an ecosystem announcement is therefore the beginning of a checklist. Ask which combinations have been tested, which operating corners were covered, who owns a field failure and how a replacement component is qualified. The economic benefit of flexibility is greatest when a second source is genuinely usable, rather than merely compatible on paper.
Commercial evidence
04 / Capacity is not one interchangeable number
Compare inputs and outputs using the same process boundary.
A packaging expansion can be described through floor space, tools, input wafers, interposer area or completed units. Those measures are not automatically comparable. A larger package consumes a different amount of processing resource from a smaller one, and a more demanding test program can change throughput even if the assembly tools are unchanged.
This is why we would not turn an unsourced monthly capacity estimate into a precise forecast of accelerator shipments. First identify the product mix and the stage being counted. Then ask whether the quoted figure refers to installed equipment, qualified capacity or actual output. Finally, determine whether memory supply and final system qualification support the same volume.
The strongest commercial evidence would connect those stages: qualified starts, acceptable packages, customer acceptance and realized cash contribution. A long waiting list can support investment, but it does not establish that a capacity addition will retain its pricing after supply catches up. Scarcity today and returns on tomorrow's equipment are different questions.
Research agenda
05 / What would change the thesis?
Ask for evidence that can overturn the integration argument.
Evidence against this thesis would include a product where monolithic integration consistently wins on cost, performance and deployment speed, or a packaging flow whose additional interfaces overwhelm its architectural benefits. The argument is not that every design should use the most elaborate package available.
Evidence in its favor would include reproducible reductions in final-test fallout, faster qualification of alternative dies and stable field reliability as package complexity rises. We would also look for customers paying for those improvements after temporary shortages ease. Sustainable value capture requires a useful service and a defensible way of charging for it.
A practical review should request a yield bridge, test-coverage summary, thermal qualification envelope and second-source plan. It should also ask who funds rejected components and how warranties allocate responsibility. These are less dramatic questions than transistor density, but they often determine whether excellent silicon becomes a durable business.
Reading the evidence
Method and limitations
This report combines public technology descriptions with original explanatory analysis. Supplier pages establish the stated capabilities and scope of their platforms; they do not independently verify production yields, prices or competitive superiority. The UCIe source establishes the scope of an interface standard, not universal interoperability in deployed products.
The chart is calculated from the assumptions printed beside it and is deliberately not presented as a market forecast. No factory interviews, private order books or proprietary production datasets were used. Sources were checked on 22 October 2026. This sample report is an analytical learning resource, not a recommendation to buy a security or select a manufacturing process.
Sources & references
- TSMC — CoWoS technologyPrimary supplier description; integration platform, not an independently audited yield series.
- TSMC — SoIC technologyPrimary description of three-dimensional silicon stacking.
- UCIe Consortium — SpecificationsPrimary standards overview; interface and compliance scope.